Dual-port memory location

ABSTRACT

The invention relates to a dual-port DRAM memory location having a capacitor and two transfer gates whose load paths are connected in series. The series connection is arranged between two data transmission lines. This arrangement serves to provide a dual-port memory location which independent of one another, can be read or written by two data processing units. The decisive advantage of the inventive memory locations in a DRAM memory architecture is the size-optimized design. The possibility of providing a memory architecture with substantially reduce space requirements. The inventive memory location is very immune to noise due to its design, due to the small number of switching elements and short length of conductor paths. The small number of transistors and short length of conductor paths also permits to reduce the time required for accessing the data. The invention also relates to a DRAM semiconductor memory having dual-port memory locations.

The invention relates to a dual-port memory cell in accordance with thepreamble of claim 1, as disclosed in U.S. Pat. No. 5,010,519 or in U.S.Pat. No. 4,292,677.

The invention likewise relates to a DRAM semiconductor memory havingdual-port memory cells.

Dual-port memory cells is a term designating all memory cells which haveprecisely two data lines, A dual-port memory cell designed as a staticmemory cell (static random access memory; SRAM) typically contains eighttransistors, in each case four selection transistors (transfer gates)and four memory transistors (inverters). These transistors are eachconnected to two word lines (selection lines) and to two bit lines (datalines). Dynamic dual-port memory cells (dynamic random access memory;DRAM) have not been known heretofore.

Future microelectronic circuits will realize complicated memoryarchitectures with numbers of transistors ranging from 10¹² to 10¹⁵. Anelementary boundary condition for economic reasons is undoubtedlyascribed here to the smallest possible area outlay of each of the memorycells on the semiconductor chip. The total number of transistors of an,individual memory cell and the wiring outlay thereof, in whichpredetermined “design rules” have to be taken into account, essentiallydetermines the size of the memory cell and, consequently, the areaoutlay of the semiconductor memory constructed from a multiplicity ofmemory cells of this type.

A further very important boundary condition, which plays a veryimportant part in particular for the semiconductor memory containing thememory cells, results from the requirement of the shortest possibleaccess time to the individual memory cells of the semiconductor memory.Shortening the effective access time is very important in particular inthe case of the fundamentally very slow dynamic memories (DRAMs), accesstime to the individual memory cells of the semiconductor memory.Shortening the effective access time is very important in particular inthe case of the fundamentally very slow dynamic memories (DRAMs), inorder not to give rise to an excessively large difference with regard tothe clock rates of the processors used as standard nowadays. The accesstime in a semiconductor memory essentially results from the propagationtime of the data signals on the word lines and from the charge reversalof the storage capacitances. However, since the effective interconnectlength increases by about 40% in the case of a semiconductor memorytransition from one-port memory cells to two-port memory cells, theundesirable result is a corresponding increase in the signal propagationtimes and, consequently, an increase in the access times. This causesadditional parasitic capacitances and resistances in the word lines anddata lines, and because of these the signal change times and,consequently, the access times to the individual memory cells areconsiderably prolonged.

The present invention is therefore based on the object of specifying adynamic dual-port memory cell with a space-sating design.

According to the invention, this object is achieved by means of adual-port memory cell having the features of patent claim 1.

In the preferred configuration, the dual-port memory cell according tothe invention in each case has a capacitive element designed as a memorytransistor and two selection transistors, whose load paths are connectedin series and this series circuit is arranged between two data lines.This arrangement makes it possible for a dual-port memory cell to beread from and written to in parallel by two date processing units.

It would also be conceivable, of course, to realize the capacitiveelement as two capacitors which are short-circuited together and are ineach case arranged between the center tap of the selection transistorsand a reference-ground potential. DRAM memory cells, in particular onaccount of their comparatively small capacitances and short respectiveline lengths, are particularly advantageous in dynamic semiconductormemories since here the corresponding memory cells can be given verysmall dimensions.

The decisive advantage of the dual-port memory cells according to theinvention in a DRAM memory architecture resides, as already mentioned,in an area-optimized design, that is to say in the possibility ofproviding a memory architecture having a distinctly reduced area outlay.In particular when the capacitive a element is designed as a CMOStransistor, each of the load path terminals of the CMOS transistor canbe short-circuited with a respective load path terminal of the selectiontransistors. It is particularly advantageous here when the terminalnodes of the CMOS transistors coincide with the terminal nodes of theselection transistors. By virtue of this saving of area-intensiveterminal nodes, the dual-port memory cell according to the inventionmanages with a very small area requirement, as a result of whichdual-port DRAM memory cells can thus be fabricated particularlycost-effectively. However, the saving of terminal nodes can alsoadvantageously be realized with capacitive elements designed ascapacitors.

In the memory cell according to the invention, both output paths of thecapacitive element have a defined potential of approximately the samemagnitude.

Functionality of this type has not been able to be ensured hitherto inconventional DRAM memory cells since here a respective terminal of thecapacitive element always “floats”, i.e. is at an undefined potential.DRAM memory cells have therefore had to be recharged at regularintervals (refresh operation). During this refresh operation, it has notbeen possible to read from or write to the DRAM memory cell, as a resultof which undefined switching states can never be completely avoided.Therefore, this abovementioned functionality has been achievablehitherto only by SRAM memory cells. The dual-port DRAM memory cellaccording to the invention makes it possible to combine theabove-described advantages of a DRAM memory cell, i.e. shorter accesstime, area optimization, etc., with the functionality of an SRAM memorycell with regard to the defined switching states thereof.

On account of its design, i.e. on account of the small number of circuitelements and short interconnect lengths, the memory cell according tothe invention is, moreover, highly insensitive to noise. The memory celltherefore exhibits a distinctly improved signal-to-noise ratio (SNR) incomparison with convention dual-port memory cells.

The smaller number of transistors and the short effective interconnectlengths additionally bring about very short access times. Moreover, theaccess time is additionally improved on account of in the reducedparasitic capacitances and resistances in the critical line path. As aresult, it is possible to provide memory systems which have a higherperformance for the same clock frequency.

In particular, the invention is particularly advantageously suitable for“multi-port semiconductor memories” having a multiplicity of dual-portDRAM memory cells according to the invention.

The subclaims are directed as preferred configurations and developmentsof the invention.

The invention is explained in more detail below using the exemplaryembodiments specified in the figures of the drawing, in which:

FIG. 1 shows the circuit diagram of a first exemplary embodiment of adual-port memory cell according to the invention;

FIG. 2 shows the circuit diagram of a second exemplary embodiment of adual-port memory cell according to the invention;

FIG. 3 shows an advantageous exemplary embodiment of a DRAMsemiconductor memory having dual-port memory cells according to theinvention.

In all the figures of the drawing, identical or functionally identicalelements are provided with the same reference symbols, unless specifiedotherwise. Hereinafter, unless specified otherwise, all dual-port DRAMmemory cells are designated as memory cells for short.

FIG. 1 shows the circuit diagram of a first exemplary embodiment of adual-port DRAM memory cell DPS according to the invention. The memorycell DPS has two selection transistors AT1, AT2 and also a capacitiveelement KE. In FIG. 1, the capacitive element KE is designed as a CMOSmemory transistor ST, whose gate terminal G is connected to a supplypotential VDD. The drain terminal D of the memory transistor ST isconnected to a first data line B1 via the load path of the firstselection transistor AT1. The source terminal S of the memory transistorST is connected to a second data line B2 via the load path of the secondselection transistor AT2. The load paths of the selection transistorsAT1, AT2 and of the memory transistor ST are thus connected in seriesand arranged between the first data line B1 and the second data line B2.The control terminals of the selection transistors AT1, AT2 areconnected to a respective word line WL1, WL2. By means of a selectionsignal on the word lines WL1, WL2, the corresponding selectiontransistors AT1, AT2 are isolated and can be driven independently.

The memory cell DPS is connected via the data lines B1, B2 to two dataprocessing units connected downstream. These data processing units maybe designed for example as a microcomputer, processor, logic circuit,bus, etc. Typically, but not necessarily, the data processing units areoperated with different clock frequencies. Data can be written to andread from the, memory cell DPS, i.e. the memory transistor ST,bidirectionally and independently of one another via the data lines B1,B2. The corresponding selection transistors AT1, AT2 car be controlledinto the on state and into an off state via the word lines WL1, WL2.

FIG. 2 shows the circuit diagram of a second exemplary embodiment of adual-port memory cell according to the invention. In the memory cell DPSin FIG. 2, the capacitive element KE has been realized by means of twostorage capacitors SK1, SK2 arranged in parallel. The storage capacitorsSK1, SK2 are designed as DRAM capacitors whose first capacitor terminals(capacitor plates) are in each case connected to one another and in eachcase to a load path terminal of the selection transistors AT1, AT2. Asupply potential VREF is applied to the respective second capacitorterminals (in a “floating” manner). It is particularly advantageous ifthe first capacitor terminals coincide with the respective load pathterminals of the assigned selection transistors AT1, AT2 in order toensure an area-optimized design.

In addition, a logic circuit or a state machine may be provided, whichregularly recharges the stored data content of the memory cell DPS. Sucha logic circuit or state machine is referred to as a refresh circuit RSin the technical jargon. In the present exemplary embodiment, thisrefresh circuit RS contains the second selection transistor AT2. In thepresent exemplary embodiment, such a refresh circuit RS is provided onlybetween the positive element KE and the second data line B2. It wouldalso be conceivable, of course, additionally or alternatively to providea (further) refresh circuit between the first data line B1 and thecapacitive element KE.

The refresh circuit RS can be formed by two sense amplifiers and aprecharge circuit in a known manner. These two sense amplifiers and theprecharge circuit could be part of the bit line decoder of thesemiconductor memory.

It is particularly advantageous if an “autorefresh circuit” RS isprovided, in the case of which the recharging of the memory cell DPS isautomated. The individual addresses of the different memory cells can becontinually generated in ascending or descending order by means of asimple clocked ring counter, which memory cells are then recharged inthe corresponding time intervals by the precharge circuit or by areference voltage source.

FIG. 3 uses a simplified circuit diagram to show an advantageousexemplary embodiment of a DRAM semiconductor memory having dual-portmemory cells according to the invention.

In a conventional DRAM memory cell, a selection transistor is in eachcase connected to a storage capacitor. The particular advantage in thecase of the memory cell according to the invention is that in each casetwo capacitors of the memory array SF, for example SK0, SK1, areinternally short-circuited together. This produces dual-port memorycells DPS in a dual-port DRAM semiconductor memory. The two ports aretotally independent of one another in this case. It is particularlyadvantageous if the two ports are separated into a read/write port and arefresh port, which is only responsible for the refresh or recharging ofthe memory array SF. In this case, the decoders for the read/write portsD_(RW-B), D_(RW-WL) may be connected to the odd-numbered data/selectionlines, while the decoders for the refresh ports D_(R-B), D_(R-WL) may beconnected to the even-numbered data/selection lines.

Although the storage density in a dual-port DRAM semiconductor memoryconfigured in this way is thereby halved in comparison with aconventional semiconductor memory, it is nonetheless still a factor of20 higher than in a conventional SRAM semiconductor memory. A dual-portDRAM semiconductor memory according to the invention which is configuredin this way can even replace a medium-sized conventional SRAMsemiconductor memory on a chip with embedded DRAM memory cells. In allthese applications, both the significantly higher storage density of asemiconductor memory configured as a DRAM in comparison with a6-transistor memory cell of an SRAM semiconductor memory and theassociated lower power loss are particularly advantageous.

The method of operation of the dual-port memory cell DPS according tothe invention is briefly described below with reference to FIG. 1:

During a write operation via the first data line D1, the first selectiontransistor AT1 is controlled into the on state. The capacitive element Kis thereby charged with the potential VDD−Vth if a digital “1” is to bewritten to the corresponding memory cell DPS, or is discharged to thepotential VSS if, for example, a digital “0” is to be written to thecorresponding memory cell DPS.

The invention exploits the fact that, for approximately identicalpotentials at the gate terminal and source terminal of the memorytransistor ST, the voltage drop UDS between source and drain terminalsis equivalent to the threshold voltage Vth thereof. Since the gateterminal of the memory transistor ST is connected to the supplypotential VDD, however, the source terminal and drain terminal of thememory transistor ST have the same potential, i.e. VS=VD=VDD−Vth for adigital “1” and VS=VD=VSS for a digital “0”. Since the drain potentialVD and the source potential VS are thus at the same potential, each ofthe data processing units can access the information stored in thememory transistor ST without a reduction in the voltage in the memorycell DPS.

Typically, in a dual-port memory cell DPS, at most one of the connecteddata processing units should be write-authorized during a writeoperation. A simple logic circuit can be used to prevent the respectiveother data processing unit from being able to write simultaneously tothe same memory cell DPS, Conversely, it is advantageously possible,however, that both data processing units connected to the dual-portmemory cell can read data from this memory cell DPS.

The invention is particularly suitable in the case of memory cellsfabricated using CMOS technology. However, the memory, cells are notrestricted to a specific transistor technology, but rather can berealized by any type of field-effect-controlled, normally on or normallyoff transistors, typically fabricated using MOS technology. However,memory cells of bipolar design would also be conceivable.

In a development, it is possible, of course, to employ all knownmeasures according to the prior art for area optimization and forshortening the access time, for example by optimizing the design rules,in order to develop the dual-port DRAM memory cell DPS according to theinvention and thus the corresponding semiconductor memory constructedfrom a multiplicity of such memory cells.

FIG. 3 shows an advantageous exemplary embodiment of a dual-portsemiconductor memory having dual-port memory cells according to theinvention.

What is claimed is:
 1. A dual-port memory cell, comprising: (a) a first selection transistor and a second selection transistor, (a1) whose load paths are arranged in series and between a first and a second data line; and (a2) whose control terminals are respectively connected to a first and a second word line, it being possible for the selection transistors to be driven independently of one another via their control terminals; and (b) a capacitive element, (b1) which has a first output terminal, which is connected to a load path terminal of the first selection transistor and a second output terminal, which is different from the first output terminal and which is connected to a load path terminal of the second selection transistor; (b2) approximately the same potential being present at the output terminals, wherein the capacitive element is designed as a memory transistor, whose load path is arranged between the series-connected load paths of the selection transistors and which can be controlled via a control terminal, to which a supply potential is applied, a voltage across the load path of the memory transistor corresponding to a turn-on voltage thereof, the first output terminal and the second output terminal of the capacitive element being directly connected to a respective load path terminal of the first selection transistor and the second selection transistor.
 2. The dual-port memory cell as claimed in claim 1, wherein the capacitive element or the memory transistor is designed as a CMOS transistor.
 3. The dual-port memory cell as claimed in claim 1, wherein the capacitive element of the dual-port memory cell can be both written to and read from via the first and/or via the second selection transistor independently of one another.
 4. The dual-port memory cell as claimed in claim 1, wherein at least one charging device is provided, which recharges the capacitance of the capacitive element in each case via at least one of the selection transistors.
 5. The dual-port memory cell as claimed in claim 4, wherein one of the selection transistors is part of the charging device.
 6. The dual-port memory cell as claimed in claim 4, wherein the charging device is part of a bit line decoder which has at least a sense amplifier and a precharge circuit, and in that the charging device has a clocked ring counter which, via its counter reading, generates an address for a respective memory cell at regular time intervals and via which the charging device automatically recharges the capacitance of the capacitive element.
 7. The dual-port memory cell as claimed in claim 1, wherein the data lines are each operated with a different clock frequency.
 8. A DRAM semiconductor memory having a multiplicity of dual-port memory cells as claimed in claim
 1. 9. The dual-port memory cell as claimed in claim 2, wherein the capacitive element of the dual-port memory cell can be both written to and read from via the first and/or via the second selection transistor independently of one another.
 10. The dual-port memory cell as claimed in claim 2, wherein at least one charging device is provided, which recharges the capacitance of the capacitive element in each case via at least one of the selection transistors.
 11. The dual-port memory cell as claimed in claim 3, wherein at least one charging device is provided, which recharges the capacitance of the capacitive element in each case via at least one of the selection transistors.
 12. The dual-port memory cell as claimed in claim 11, wherein one of the selection transistors is part of the charging device.
 13. The dual-port memory cell as claimed in claim 5, wherein the charging device is part of a bit line decoder which has at least a sense amplifier and a precharge circuit, and in that the charging device has a clocked ring counter which, via its counter reading, generates an address for a respective memory cell at regular time intervals and via which the charging device automatically recharges the capacitance of the capacitive element.
 14. The dual-port memory cell as claimed in claim 2, wherein the data lines are each operated with a different clock frequency.
 15. The dual-port memory cell as claimed in claim 3, wherein the data lines are each operated with a different clock frequency.
 16. The dual-port memory cell as claimed in claim 4, wherein the data lines are each operated with a different clock frequency.
 17. A DRAM semiconductor memory having a multiplicity of dual-port memory cells as claimed in claim
 2. 18. A DRAM semiconductor memory having a multiplicity of dual-port memory cells as claimed in claim
 3. 19. A DRAM semiconductor memory having a multiplicity of dual-port memory cells as claimed in claim
 4. 20. A DRAM semiconductor memory having a multiplicity of dual-port memory cells as claimed in claim
 5. 